A semiconductor package is a structure used to accommodate at least one integrated circuit component such as semiconductor chip and preferably made compact in size. In correspondence with this goal, there is a type of small scale semiconductor package, named chip scale package (CSP), which has a size substantially equal to or slightly larger than that of the chip incorporated therein.
U.S. Pat. No. 6,287,893 discloses a chip scale package which forms a plurality of build-up layers directly on a semiconductor chip without using a chip carrier such as substrate or lead frame for accommodating the chip. As shown in FIG. 5, the plurality of build-up layers formed on an active surface 100 of the chip 10 include: a dielectric layer 11 disposed over the active surface 100 of the chip 10 and formed with a plurality of vias 110 for exposing bond pads 101 formed on the chip 10; and a plurality of conductive traces 12 formed on the dielectric layer 11 and electrically connected to the exposed bond pads 101 of the chip 10. A solder mask layer 13 is applied over the conductive traces 12 and formed with a plurality of openings 130, allowing predetermined portions of the conductive traces 12 to be exposed via the openings 130 and bonded to solder balls 14 which serve as input/output (I/O) connections for electrically connecting the chip 10 to an external device such as printed circuit board (not shown). This chip scale package, however, is defective of not able to provide more surface area, which is limited in accordance with the chip size, for accommodating more solder balls required for the external electrical connection.
Accordingly, U.S. Pat. No. 6,271,469 discloses another package structure which forms the build-up layers on an encapsulated chip so as to provide additional surface area for external I/O connections. As shown in FIG. 6, this package structure utilizes an encapsulation body 15 for encapsulating a non-active surface 102 and side surfaces 103 of the chip 10, allowing the active surface 100 of the chip 10 to be exposed and flush with a surface 150 of the encapsulation body 15. After the dielectric layer 11 (hereinafter referred to as “first dielectric layer”) and conductive traces 12 (hereinafter referred to as “first conductive traces”) are formed on the chip 10, a second dielectric layer 16 is disposed over the first conductive traces 12 and formed with a plurality of vias 160 for exposing predetermined portions of the first conductive traces 12. A plurality of second conductive traces 17 are formed on the second dielectric layer 16 and electrically connected to the exposed portions of the first conductive traces 12. Then, the solder mask layer 13 is applied over the second conductive traces 17, allowing predetermined portions of the second conductive traces 17 to be exposed via the openings 130 of the solder mask layer 13 and bonded to the solder balls 14.
However, a significant drawback incurred by the above chip scale package and the encapsulated package structure is that when a laser drilling technique is employed to form vias through the first dielectric layer for exposing the bond pads on the chip, the bond pads underneath the first dielectric layer cannot be easily and precisely recognized by laser in position, making the fabricated vias not able to accurately correspond to the positions of the bond pads. As a result, the bond pads on the chip cannot be completely exposed, and the incompletely-exposed bond pads would degrade their electrical connection with the first conductive traces formed on the first dielectric layer, thereby damaging production yield of the fabricated packages. Moreover, as shown in FIG. 6, the chip is entirely encapsulated by the encapsulation body, making heat produced from the chip not able to be effectively dissipated, which may damage the chip by overheat.
Therefore, the problem to be solved herein is to provide a thermally enhanced semiconductor package which can effectively dissipate heat from an incorporated chip and assure electrical connection between conductive traces and bond pads formed on the chip.